1. Field of the Invention
The present invention relates to a thin film magnetic memory device, and particularly to a thin film magnetic memory device provided with memory cells having MTJs (magnetic tunnel junctions)
2. Description of the Background Art
Attention is being given to an MRAM device as a memory device, which can nonvolatilely store data with low power consumption. The MRAM device is a memory device, in which a plurality of thin film magnetic members are formed in a semiconductor integrated circuit for nonvolatilely storing data, and random access to each thin film magnetic member is allowed.
Particularly, in recent years, it has been announced that a performance of the MRAM device can be dramatically improved by using the thin film magnetic members, which utilize the magnetic tunnel junctions, as memory cells. The MRAM device with memory cells having the magnetic tunnel junctions has been disclosed in technical references such as xe2x80x9cA 10 ns Read and Write Non-Volatile Memory Array Using a Magnetic Tunnel Junction and FET Switch in Each Cellxe2x80x9d, ISSCC Digest of Technical Papers, TA7.2, February 2000, xe2x80x9cNonvolatile RAM based on Magnetic Tunnel Junction Elementsxe2x80x9d, ISSCC Digest of Technical Papers, TA7.3, February 2000, and xe2x80x9cA 256 kb 3.0V 1T1MTJ Nonvolatile Magnetoresistive RAMxe2x80x9d, ISSCC Digest of Technical Papers, TA7.6, February 2001.
FIG. 15 conceptually shows a structure of a memory cell, which has a magnetic tunneling junction, and may be merely referred to as an xe2x80x9cMTJ memory cellxe2x80x9d hereinafter.
Referring to FIG. 15, a MTJ memory cell includes a tunneling magneto-resistance element TMR having an electric resistance, which is variable in accordance with a data level of magnetically written storage data, and an access transistor ATR. Access transistor ATR is located between a bit line BL and a source line SRL, and is connected in series to tunneling magneto-resistance element TMR. Typically, access transistor ATR is formed of a field-effect transistor arranged on a semiconductor substrate.
For the MTJ memory cell, the device includes bit line BL and a digit line DL for carrying a data write current in different directions during a data write operation, respectively, a word line WL for instructing data reading, and source line SRL for puling down tunneling magneto-resistance element TMR to a ground voltage Vss during a data read operation. In the data read operation, tunneling magneto-resistance element TMR is electrically coupled between source line SRL carrying ground voltage Vss and bit line BL in response to turn-on of access transistor ATR.
FIG. 16 conceptually shows an operation of writing data in the MTJ memory cell.
Referring to FIG. 16, tunneling magneto-resistance element TMR has a ferromagnetic material layer FL, which has a fixed and uniform magnetization direction, and may be merely referred to as a xe2x80x9cfixed magnetic layerxe2x80x9d hereinafter, and a ferromagnetic material layer VL, which is magnetized in a direction depending on an externally applied magnetic field, and may be merely referred to as a xe2x80x9cfree magnetic layerxe2x80x9d hereinafter. A tunneling barrier (tunneling film) TB formed of an insulator film is disposed between fixed magnetic layer FL and free magnetic layer VL. Free magnetic layer VL is magnetized in the same direction as fixed magnetic layer FL or in the opposite direction in accordance with the level of the storage data to be written. Fixed magnetic layer FL, tunneling barrier TB and free magnetic layer VL form a magnetic tunnel junction.
Tunneling magneto-resistance element TMR has an electric resistance, which is variable depending on a correlation in magnetization direction between fixed magnetic layer FL and free magnetic layer VL. More specifically, the electric resistance value of tunneling magneto-resistance element TMR takes a minimum value Rmin when the magnetization directions of fixed magnetic layer FL and free magnetic layer VL are parallel to each other. When the magnetization directions of them are opposite (anti-parallel) to each other, the above electric resistance value takes a maximum value Rmax.
In the data write operation, word line WL is inactive, and access transistor ATR is off. In this state, the data write currents for magnetizing free magnetic layer VL are supplied to bit line BL and digit line DL in directions depending on the level of write data, respectively.
FIG. 17 conceptually shows a relationship between the data write current and the magnetization direction of the tunneling magneto-resistance element in the data write operation.
Referring to FIG. 17, an abscissa H(EA) gives a magnetic field, which is applied in an easy axis (EA) to free magnetic layer VL of tunneling magneto-resistance element TMR. An ordinate H(HA) indicates a magnetic field acting in a hard axis (HA) on free magnetic layer VL. Magnetic fields H(EA) and H(HA) correspond to two magnetic fields produced by currents flowing through bit line BL and digit line DL, respectively.
In the MTJ memory cell, the fixed magnetization direction of fixed magnetic layer FL is parallel to the easy axis of free magnetic layer VL, and free magnetic layer VL is magnetized in the easy axis direction, and particularly in the same parallel direction, which is the same direction as fixed magnetic layer FL, or in the anti-parallel direction, which is opposite to the above direction, depending on the level (xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d) of the storage data. The MTJ memory cell can selectively store data (xe2x80x9c1xe2x80x9d and xe2x80x9c0xe2x80x9d) of one bit corresponding to the two magnetization directions of free magnetic layer VL.
The magnetization direction of free magnetic layer VL can be rewritten only when a sum of applied magnetic fields H(EA) and H(HA) falls within a region outside an asteroid characteristic line shown in FIG. 17. Therefore, the magnetization direction of free magnetic layer VL does not switch when the data write magnetic fields applied thereto have intensities corresponding to a region inside the asteroid characteristic line.
As can be seen from the asteroid characteristic line, the magnetization threshold required for switching the magnetization direction along the easy axis can be lowered by applying the magnetic field in the direction of the hard axis to free magnetic layer VL.
When the operation point in the data write operation is designed, for example, as shown in FIG. 17, the data write magnetic field in the MTJ cell selected as a data write target is designed such that the data write magnetic field in the direction of the easy axis has an intensity of HWR. Thus, the data write current flowing through bit line BL or digit line DL is designed to take a value, which can provide the data write magnetic field of HWR. In general, data write magnetic field HWR is represented by a sum of a switching magnetic field HSW required for switching the magnetization direction and a margin xcex94H. Thus, it is represented by an expression of HWR=HSW+xcex94H.
For rewriting the storage data of the MTJ memory cell, i.e., the magnetization direction of tunneling magneto-resistance element TMR, it is necessary to pass the data write currents at a predetermined level or higher through digit line DL and bit line BL. Thereby, free magnetic layer VL in tunneling magneto-resistance element TMR is magnetized in the parallel direction as fixed magnetic layer FL or anti-parallel direction in accordance with the direction of the data write magnetic field along the easy axis (EA). The magnetization direction, which was once written into tunneling magneto-resistance element TMR, and thus the storage data of MTJ memory cell is held nonvolatilely until next data writing is executed.
FIG. 18 conceptually shows an operation of reading data from the MTJ memory cell.
Referring to FIG. 18, access transistor ATR is turned on in response to activation of word line WL in the data read operation. Thereby, tunneling magneto-resistance element TMR is electrically coupled to bit line BL while being pulled down with ground voltage GND.
In this state, bit line BL is pulled up with a predetermined voltage, whereby a current path including bit line BL and tunneling magneto-resistance element TMR carries a memory cell current Icell corresponding to storage data of the MTJ memory cell. For example, this memory cell current Icell is compared with a predetermined reference current, whereby storage data can be read out from the MTJ memory cell.
As described above, the electric resistance of tunneling magneto-resistance element TMR is variable in accordance with the magnetization direction, which is rewritable by the data write magnetic field applied thereto. Therefore, nonvolatile data storage can be executed by establishing a correlation of electric resistances Rmax of Rmin of tunneling magneto-resistance element TMR with respect to levels (xe2x80x9c1xe2x80x9d and xe2x80x9c0xe2x80x9d) of the storage data.
As described above, the MRAM device executes the data storage by utilizing a difference xcex94R (=Rmaxxe2x88x92Rmin) in junction resistance of tunneling magneto-resistance element TMR corresponding to a difference between storage data levels. Thus, the data read operation is executed based on the detection of passing current Icell of the selected memory cell.
For example, U.S. Pat. No. 6,205,073B 1 (which will be merely referred to as a xe2x80x9cprior artxe2x80x9d hereinafter) has disclosed a structure for taking out a memory cell passing current by a current conveyor.
FIG. 19 is a circuit diagram showing a structure of a data read circuit according to the prior art.
Referring to FIG. 19, when data reading is to be performed, access transistor ATR in a selected memory cell 501 is turned on in accordance with activation of word line WL. Further, tunneling magneto-resistance element TMR (electric resistance Rmtj) of selected memory cell 501 is connected between a data readout line 503 and ground voltage Vss via a transistor switch 502, which is turned on by a column decoder.
The data read circuit according to the prior art includes current conveyors 505 and 510, which are arranged in two positions or stages with respect to data readout line 503, respectively.
Current conveyor 505 is arranged between data readout line 503 and a junction 508, and has a sense amplifier 506 and a transistor 507. Transistor 507 is connected between data readout line 503 and junction 508. Sense amplifier 506 amplifies a voltage difference between a predetermined bias voltage Vb1 and data readout line 503, and applies the amplified difference to a gate of transistor 507. Junction 508 is supplied with a constant current Is from a current source 509.
Current conveyor 510 is arranged between junction 508 and ground voltage Vss, and has a sense amplifier 511 and a transistor 512. Transistor 512 is connected between junction 508 and ground voltage Vss. Sense amplifier 511 amplifies a voltage difference between a predetermined bias voltage Vb2 and junction 508, and applies it to an output node 513. Output node 513 is connected to a gate of transistor 512.
By negative feedback operations, current conveyors 505 and 510 clamp the voltages on data readout line 503 and junction 508 at first and second bias voltages Vb1 and Vb2, respectively, and can produce a voltage Vo corresponding to passing current Icell of selected memory cell 501 on output node 513. Thus, passing current Icell of selected memory cell 501 can be detected while clamping a voltage applied to tunneling magneto-resistance element TMR at bias voltage Vb1, and thereby keeping stable electric resistance characteristics in tunneling magneto-resistance element TMR.
However, the data read circuit according to the prior art requires sense amplifiers 506 and 511, and a relatively large number of circuit elements are arranged in the circuit. Practically, the data reading is performed based on complementary comparing operations so that two data read circuit systems of the same structures are required, which further increases the number of circuit elements. Accordingly, variations in characteristics between circuit elements, which occur in a manufacturing process, may adversely affect data read accuracy.
Further, the circuit structure shown in FIG. 19 does not provide sufficiently high output voltage Vo on output node 513. Therefore, it is necessary to detect output voltage Vo with high accuracy.
Further, the negative feedback circuit causes unstable operations immediately after the power-on so that sense amplifiers 506 and 511 must be always supplied with operation currents. This increases a standby current of the data read circuit, and thus increases power consumption.
Further, output voltage Vo obtained on node No is affected by variations in resistance value (Rmtj) of tunneling magneto-resistance element TMR caused by variations in manufacturing of the MTJ memory cells. For increasing the accuracy of data reading, it is necessary to give consideration to a structure, which can compensate for lowering of the data read accuracy in accordance with variations caused in electric resistance characteristics of the MTJ memory cells due to variations in manufacturing process.
An object of the invention is to provide a structure of a thin film magnetic memory device, which can execute accurate data reading by a simple circuit structure.
In summary, a thin film magnetic memory device includes a plurality of memory cells, first and second data lines complementary to each other, and a differential amplifier portion. Each of the plurality of memory cells has an electric resistance according to magnetically written storage data. The differential amplifier portion performs data reading according to a difference between passing currents of the first and second data lines. In a data read operation, the first and second data lines are electrically coupled to a fixed voltage via a selected memory cell among the plurality of memory cells and a reference cell provided as a comparison target of the selected memory cell, respectively. The differential amplifier portion includes a current supply circuit arranged between a power supply voltage and first and second nodes for supplying the same operation current to the first and second nodes at least in the data read operation, and a current amplifier circuit for electrically coupling the first and second nodes to the first and second data lines, respectively, and converting a passing current difference occurring between the first and second data lines into a voltage difference between the first and second nodes so that each of the first and second data lines may be clamped at a predetermined voltage not exceeding a reference voltage.
Preferably, the differential amplifier portion further includes a current supply transistor electrically coupled between the power supply voltage and an internal node, and being turned on to supply the operation current in the data read operation. The current supply circuit has first and second transistors electrically coupled between the internal node and the first and second nodes, respectively, and each having a gate connected to the first node. The current amplifier circuit has a third transistor electrically coupled between the first node and the first data line with receiving the reference voltage on its gate, and a fourth transistor electrically coupled between the second node and the second data line with receiving the reference voltage on its gate.
According to a major advantage of the invention, therefore, the operation current of the differential amplifier portion is used as the passing currents of the selected memory cell and the reference cell so that the circuit elements of a data read circuit system can be reduced in number. Further, the passing current difference between the selected memory cell and the reference memory cell is amplified and converted into the voltage difference. Therefore, data reading can be performed with high accuracy.
Preferably, the current supply circuit has a first current mirror circuit for supplying the same current to the first and third nodes, and a second current mirror circuit for supplying the same current to the second and fourth nodes. The current amplifier circuit has a first converting circuit provided between the first and fourth node and the first data line, and for producing on the first node a voltage corresponding to the passing current of the first data line, and a second converting circuit provided between the second and third nodes and the second data line, and for producing on the second node a voltage corresponding to the passing current of the second data line.
According to the above structure, the differential amplifier portion formed of two complementary current mirror circuits can keep a balance between load capacities of the first and second nodes when performing differential amplification. Therefore, a data read time can be constant independently of the level of the read data. Further, a DC gain in the differential amplifying operation is large so that the data read operation can be stable.
According to another aspect of the invention, a thin film magnetic memory device includes a plurality of memory cells, a reference cell, a first data line and a data read circuit. Each of the plurality of memory cells has one of first and second electric resistances according to magnetically written storage data. The reference cell has an electric resistance intermediate between the first and second electric resistances, and is electrically coupled between first and second voltages at least in a data read operation. The first data line is electrically coupled between the first and second voltages via a selected memory cell corresponding to a selected address in the data read operation. The data read circuit is provided for performing data reading according to a difference between passing currents of the selected memory cell and the reference cell, and includes a data line voltage clamping portion. The data line voltage clamping portion clamps the first data line at a predetermined voltage based on the passing current of the reference cell in the data read operation.
The thin film magnetic memory device described above can clamp the voltage on the data line connected to the selected memory cell when executing the data read operation. Therefore, the data reading can be performed fast without charging and discharging the above data line having a relatively large parasitic capacity. Further, the clamping of the data line voltage can be performed based on the passing current of the reference cell, i.e., an actual electric resistance so that the data read accuracy can be ensured by following variations in electric resistance characteristics due to variations in manufacturing process.
Preferably, the data line voltage clamping portion clamps the first data line at the predetermined voltage prior to the data reading.
Even before the data reading, the data line is clamped at the predetermined voltage similar to that in the data read operation. Therefore, charging and discharging of the data line are not required even before the start of data reading. Consequently, the data read operation can be performed further fast.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.